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MC908GZ48MFJE

8-BIT, FLASH, 8MHz, MICROCONTROLLER, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, LQFP-32

器件类别:嵌入式处理器和控制器    微控制器和处理器   

厂商名称:FREESCALE (NXP)

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
Objectid
2069911779
零件包装代码
QFP
包装说明
LQFP, QFP32,.35SQ,32
针数
32
Reach Compliance Code
unknown
ECCN代码
3A991
具有ADC
YES
其他特性
OPERATES AT 3.3V SUPPLY @ 4MHZ
地址总线宽度
位大小
8
CPU系列
68HC08
最大时钟频率
32 MHz
DAC 通道
NO
DMA 通道
NO
外部数据总线宽度
JESD-30 代码
S-PQFP-G32
JESD-609代码
e3
长度
7 mm
湿度敏感等级
3
I/O 线路数量
37
端子数量
32
最高工作温度
125 °C
最低工作温度
-40 °C
PWM 通道
YES
封装主体材料
PLASTIC/EPOXY
封装代码
LQFP
封装等效代码
QFP32,.35SQ,32
封装形状
SQUARE
封装形式
FLATPACK, LOW PROFILE
峰值回流温度(摄氏度)
260
电源
3.3/5 V
认证状态
Not Qualified
RAM(字节)
1536
ROM(单词)
49152
ROM可编程性
FLASH
座面最大高度
1.6 mm
速度
8 MHz
最大压摆率
30 mA
最大供电电压
5.5 V
最小供电电压
4.5 V
标称供电电压
5 V
表面贴装
YES
技术
HCMOS
温度等级
AUTOMOTIVE
端子面层
MATTE TIN
端子形式
GULL WING
端子节距
0.8 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
40
宽度
7 mm
uPs/uCs/外围集成电路类型
MICROCONTROLLER
文档预览
MC68HC908GZ60
MC68HC908GZ48
MC68HC908GZ32
Data Sheet
M68HC08
Microcontrollers
MC68HC908GZ60
Rev. 6.0
04/2007
freescale.com
MC68HC908GZ60
MC68HC908GZ48
MC68HC908GZ32
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2005, 2006, 2007. All rights reserved.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
3
Revision History
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
April,
2004
Revision
Level
N/A
Initial release
9.7.3 Keyboard Interrupt Polarity Register — Corrected the bit description of
the KBIP7–KBIP0 bits.
14.8.8 ESCI Prescaler Register — Reworked note under PDS2–PDS0
description for clarity.
Table 22-1. MC Order Numbers — Corrected order numbers.
May,
2004
1.0
Figure 22-1. Device Numbering System — Reworked diagram to reflect
correct order numbers.
Table A-1. MC Order Numbers — Corrected order numbers.
Figure A-3. Device Numbering System — Reworked diagram to reflect
correct order numbers.
B.4 Ordering Information — Corrected order numbers.
Figure B-3. Device Numbering System — Reworked diagram to reflect
correct order numbers.
Reformatted to Freescale publication standards
June,
2005
2.0
Table 14-6. ESCI LIN Control Bits — Corrected Functionality entries
14.9.1 ESCI Arbiter Control Register — Corrected bit ACLK bit description
14.9.3 Bit Time Measurement — Corrected definition for ACLK bit
March,
2006
3.0
10.5 Clock Generator Module (CGM) — Updated description to remove
erroneous information.
Added section 1.5.15 Unused Pin Termination
Chapter 13 Input/Output (I/O) Ports — Replaced note
Table 14-6. ESCI LIN Control Bits — Updated functionality column.
18.6 TIM1 During Break Interrupts — Updated first paragraph for clarity.
19.6 TIM2 During Break Interrupts — Updated first paragraph for clarity.
July,
2006
4.0
20.2.1.2 TIM During Break Interrupts — Updated first paragraph for clarity.
Figure 20-10. Normal Monitor Mode Circuit and Figure 20-11. Forced Monitor
Mode — Changed capacitor values
21.5 5.0-Vdc Electrical Characteristics — Updated minimum value for
low-voltage inhibit, trip rising voltage (VTRIPR).
21.9.2 CGM Component Information — Updated values for feedback bias
resistor
Description
Page
Number(s)
N/A
119
212
329
329
342
342
346
346
Throughout
211
215
216
122
31
169
213
270
290
302
307
317
322
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
4
Freescale Semiconductor
Revision History (Continued)
Date
Revision
Level
Description
12.2 Features — Corrected timer link connection from TIM2 channel 0 to
TIM1 channel 0.
October,
2006
5.0
12.9 Timer Link — Corrected timer link connection from TIM2 channel 0 to
TIM1 channel 0.
21.5 5.0-Vdc Electrical Characteristics and
21.6 3.3-Vdc Electrical Characteristics — Updated DC injection current
specification.
Figure 2-2. Control, Status, and Data Registers
— Changed TBMCLKSEL to
TMBCLKSEL to be compatible with development tool nomenclature
Chapter 5 Configuration Register (CONFIG)
— Changed COPCLK to
CGMXCLK and TBMCLKSEL to TMBCLKSEL to be compatible with
development tool nomenclature
10.6.2 Stop Mode
— Changed COPCLK to CGMXCLK
Figure 14-3. ESCI Module Block Diagram
— Changed BUS_CLK to BUS
CLOCK and removed reference to 4xBUSCLK
April,
2007
14.4.2 Transmitter
— Changed ESCIBDSRC to SCIBDSRC
6.0
14.9.1 ESCI Arbiter Control Register
and
14.9.3 Bit Time Measurement
Replaced one quarter with one half in the definition for ACLK = 1
Figure 17-1. Timebase Block Diagram, 17.5 TBM Interrupt Rate,
and
Table
17-1. Timebase Divider Selection
— Changed TBMCLKSEL to TMBCLKSEL
to be compatible with development tool nomenclature
21.9 Clock Generation Module (CGM) Characteristics
— Updated section to
include the following:
21.9.1 CGM Operating Conditions
21.9.2 CGM Component Information
21.9.3 CGM Acquisition/Lock Time Information
Page
Number(s)
135
147
317
319
37
91
92
93
125
192
194
217
218
260
261
322
322
323
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
5
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